On a call with analysts, Micron’s chief technology officer stated that 4F² DRAM offers little density advantage over 6F² designs and said 3D DRAM could be a better option at the leading edge.
- The company expects its 1-delta DRAM and G11 NAND technologies to begin ramping in the second half of 2027.
- Micron introduced vertical HBM, which places memory directly on top of a processor to increase bandwidth.
- Micron said memory supply could remain tight for at least two years, with no clear point when supply and demand return to balance.
Micron Technology (MU) told analysts on Wednesday that a DRAM design some rivals are pursuing offers no real density benefit. Micron’s president and chief technology and products officer, Scott DeBoer, said 3D DRAM will take its place when the economics work.
On a call with analysts, DeBoer also laid out new DRAM and NAND nodes for the second half of 2027 and introduced a stacked-memory product line called vertical HBM.
This [vertical HBM] is a implementation of memory capability directly on top of processing units and is a key element of our customer partnership going forward in delivering this solution which provides ultimate bandwidth in combination with co-design and also still utilizing HBM around the edges of in many cases of the XPUs.
– Scott DeBoer, President and Chief Technology and Products Officer, Micron Technology
MU stock rose nearly 2% in midday trade on Wednesday. On Stocktwits, retail sentiment around Micron continued to trend in ‘bullish’ territory alongside ‘normal’ levels of chatter over the past day. The stock price is almost 40% below its record high of over $1250 seen in June.
Micron Questions The Benefits Of 4F² DRAM
UBS analyst Tim Arcuri asked why Micron sees no viable path for 4F² DRAM when some competitors are pursuing the design. The terms 4F² and 6F² refer to the area occupied by each memory cell.
DeBoer said the key factor in DRAM density is the spacing between capacitors, rather than the layout of the memory cell itself. He called the claimed density advantage of 4F² over 6F² “a bit of a myth.”
He stated that Micron can build 4F² DRAM at older technology nodes, but doing so brings higher costs and greater complexity. According to him, at the leading edge, the design faces “fundamental” scaling problems.
There's fundamental problems with 4F squared scaling. That ultimately will lead to 3D DRAM coming in instead of 4F squared.
– Scott DeBoer, President and Chief Technology and Products Officer, Micron Technology
Micron’s roadmap places 3D DRAM between its 1-zeta and 1-eta nodes. DeBoer described it as a parallel development path whose timing will depend on the economics. The goal is to have the technology “ready to implement” when it makes business sense.
DeBoer said Micron invented 4F² and has studied the design for two decades, but has chosen not to pursue it commercially.
New DRAM And NAND Nodes Target Second Half Of 2027
DeBoer called Micron’s fifth consecutive node as industry-leading, and said it is scheduled to ramp in the second half of 2027, starting in Boise. He said it is expected to deliver a mid-20% improvement in bit density and is designed for HBM5 and vertical HBM. Samsung is reportedly targeting late 2027 for its equivalent node.
DeBoer added that development of 1-epsilon DRAM, which uses wafer bonding, is “well underway.” According to him, the 1-zeta and 1-eta nodes remain in the pathfinding stage, with high-NADe extreme ultraviolet lithography and new materials among the technologies being explored.
DeBoer also announced that Micron plans to move from Gen 9 to G11, skipping a generation. He called it “the world’s most advanced Nand.” The technology is scheduled to ramp in the second half of 2027, with more than 400 layers, twice Gen 9’s bit density and 1.5 times its input/output speed. It uses wafer-on-wafer bonding.
Vertical HBM Targets Higher Bandwidth
Micron said its HBM4 memory is in high-volume production, with each stack delivering 2.8 terabytes per second of bandwidth. DeBoer said roughly 100 such stacks could match the world’s total internet bandwidth.
The company’s next step is vertical HBM, which places memory directly on top of a processor to increase bandwidth. DeBoer said hybrid bonding, a process that connects chips at much tighter spacing, will be essential to achieving the required performance.
Micron is also developing vertical edge inference memory, which stacks low-power DRAM on a logic die. The product is aimed at devices such as robots and cars. DeBoer said it can deliver more bandwidth than processing-in-memory designs, which place computing functions inside the memory chip. Micron is pursuing both approaches.
Both vertical products use more wafers per bit than conventional DRAM. DeBoer said the “trade ratios continue to increase,” a trend that adds pressure to conventional memory supply.
Demand and supply
Micron expects memory supply to remain tight for at least two years, DeBoer said, citing CEO Sanjay Mehrotra. He added that the company does not see a point when supply and demand come back into balance.
“Inherently more memory does equal better system performance,” he said, adding that “memory has become the AI bottleneck.”
DeBoer also outlined how Micron is using AI internally to accelerate development. The company cut the time from silicon development to tape-out for a new data center solid-state drive controller by half. It also developed an entire data center SSD about 60% faster than the previous generation.
He pointed to Micron’s $10 billion, 10-year research lab commitment and a Meta white paper on LPDDR6 as further examples of its work. DeBoer closed by saying Micron is in “its strongest position in history.”
Micron reported record revenue of $54.23 billion in its last quarter and forecast $61.5 billion for the next quarter. The company ranks third in high-bandwidth memory, behind Samsung and SK Hynix (SKHY).
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